Wafer Level Package Using Silicon Via Contacts for Cmos Image Sensor and Method of Fabricating the Same

ABSTRACT

The present invention relates to a wafer level package of a CMOS image sensor using silicon via contacts and a method of manufacturing the same. A wafer level package of a CMOS image sensor includes: a wafer where image sensor elements including a plurality of electrode pads are formed; a transparent substrate attached to a front side of the wafer; a via hole formed from a back side of the wafer to underneath of a plurality of electrode pads of the front side; a passivation layer formed on a remaining portion except the underneath of the electrode pads in the via hole and whole back side of the wafer; a via contact formed in the via hole; and a solder bump formed on the via contact of the back side of the wafer.

TECHNICAL FIELD

The present invention relates to a wafer level package of acomplementary metal oxide semiconductor (CMOS) image sensor and a methodof manufacturing the same; and, more particularly, to a wafer levelpackage of a CMOS image sensor and a method of manufacturing the same byforming a front side of a wafer where image sensing elements including asensing unit and an electrode pad are formed and forming a silicon viacontact which directly attaches the electrode pad to a back side of thewafer and by forming a solder bump on an exposed silicon via contact ofthe back side of the wafer and attaching the solder bump to a printedcircuit board (PCB).

BACKGROUND ART

Generally, an image sensor is a semiconductor module for converting anoptical image to an electric signal, and used to store an image signaland transfer it to a display device. The image sensor is roughlyclassified into two classes, i.e., one is a charge-coupled device (CCD)image sensor and the other is a CMOS image sensor. The CCD image sensortransfers an electric charge by continually controlling a depth of apotential well in the direction of the charge transfer. The CMOS imagesensor performs an image sensing by using one or more transistor and aphoto diode included in a pixel unit cell, wherein the photo diode actsas a photo sensor.

Since the CCD image sensor has less noise and better image quality incomparison with the CMOS image sensor, the CCD image sensor is suitablefor a digital camera. On the contrary, the CMOS image sensor hasgenerally less power consumption and lower manufacturing cost and can beeasily integrated to a peripheral circuit chip in comparison with theCCD image sensor. Particularly, the CMOS image sensor can be producedusing conventional technologies for manufacturing semiconductors, and itis easily integrated to a peripheral system which performs operationssuch as amplification and signal processing, resulting in a reduction ofthe manufacturing cost. Further, the CMOS image sensor has a highoperational speed and power consumption of the CMOS image sensor isabout 1% of that of the CCD image sensor. Therefore, the CMOS imagesensor has been applied to a camera for a cellular phone and a personaldigital assistant (PDA). However, as technology of the CMOS image sensorhas been developed, the technical boundary between the CMOS image sensorand the CCD image sensor is demolished.

That is, the speed of technical development of the CMOS image sensor hasbeen greatly increased. For instance, the CMOS image sensor was used asan image sensor for a VGA camera phone; however, recently, the CMOSimage sensor is used as an image sensor for over 2-megapixel cameraphone.

Meanwhile, until now, a modularization has been processed in the mannerof wire bonding by using a package for an image sensor chip. However,according to the wire bonding process, the foreign materials aregenerated to cause an image defect of a sensor window, and so theproduction yield during module assembly is decreased and a depth, awidth and a height of the module are increased, making it difficult toreduce a size of the module.

Recently, the chip on flexible PCB (COF) technology is beginning to beapplied as a new method for modularizing cameras. Herein, the COFtechnology uses an anisotropic conductive film (ACF) which is applied toa technology for manufacturing a liquid crystal display (LCD) panel. TheKorean patent application No. 2003-0069321 discloses the flip chip Aubumping process which finishes the packaging process at a wafer state,and also an imaging element package to which the COF mount technology isapplied and the method for manufacturing the same.

FIG. 1 is a diagram showing a camera module using a CMOS image sensor(CIS) chip according to the prior art.

As shown in FIG. 1, bonding of a CIS chip 105 is completed by connectinga gold stud bump 120 b formed on the CIS chip 105 to an externalelectrode pad 120 a of a flexible printed circuit board (FPC) 103through a conductive ball of an anisotropic conductive film 104.Thereafter, the camera module is completed by adding a lens 100, a lenshousing 101 and an infrared filter (not shown). In this manner, the CISchip 105 can be directly attached to the FPC 103 without an additionalpackage for the CIS by using the anisotropic conductive film.

However, in the above-mentioned flip chip method, since a sensor window106 for image sensing is inevitably faced to the anisotropic conductivefilm 104, the foreign materials generated from the anisotropicconductive film 104 and FPC enter the sensor window 106 of the CIS chip,when the CIS chip 105 is attached to the FPC 103. Therefore, theproduction yield is greatly decreased.

For solving the above-mentioned problem, Shellcase, an Israelicorporation, has developed a new technology. According to the technologyof Shellcase, a wafer is etched and an electrode, which is connected toan electrode pad formed on the same surface that a sensing unit of thewafer is formed, is extended to the back side of the wafer (oppositeside of the sensing unit) so that the sensing unit of CIS chip isdirected to an opposite direction of an anisotropic film in order to beattached to an FPC.

FIGS. 2 to 6 are cross-sectional views showing the process of Shellcasefor manufacturing the CIS package.

Referring to FIG. 2, through a predetermined manufacturing process, CISelements such as an electrode pad 201 and a sensing unit 202 for imagesensing are formed on a front side 200 a of a wafer 200. Aftercompleting the process for manufacturing the image sensor packagedescribed below, chips are separated by dicing along a cutting lane 250.

Next, as shown in FIG. 3, a first glass substrate 204 is added on thefront side of the wafer 200 by using an epoxy 203.

Next, referring to FIG. 4, after etching the wafer 200 from a back side200 b until the electrode pad 201 which exists on the front side of thewafer 200 is exposed as shown in a circle 206, a second glass substrate207 is attached by using an epoxy 203 a.

Next, as shown in FIG. 5, after etching the second glass substrate 207,an external electrode 208 is formed by forming and patterning anelectric conductor. The external electrode 208 forms a T-contact 209with the electrode pad 201.

Next, as shown in FIG. 6, after exposing a region, where a solder bumpis to be formed, by depositing and patterning an insulating layer 211 onthe second glass substrate 207 and the external electrode 208, a solderbump 210 is formed and chips are separated from one another by dicingthe wafer 200 along the cutting lane 250. Thereafter, through apredetermined manufacturing process, an imaging device module such as acamera is assembled.

However, in the above-mentioned method for manufacturing image sensorpackage, a region of the T-contact 209 may be cracked and thus, acontact failure easily occurs. Further, the manufacturing process iscomplicated, e.g., a patterning process for forming an externalelectrode should be performed and an insulating layer for protecting anexternal electrode or for solder masking should be formed. Accordingly,a production yield is decreased.

DISCLOSURE OF INVENTION Technical Problem

The present invention has been proposed in order to overcome theabove-described problems in the related art. It is, therefore, an objectof the present invention to prevent foreign materials from entering animage sensing unit.

It is another object of the present invention to provide a chip scalepackage of an image sensor having a thin image sensor module.

Technical Solution

In accordance with one aspect of the present invention, there isprovided a method of wafer level packaging of a CMOS image sensor,comprising the steps of: attaching a transparent substrate to a frontside of a wafer where image sensor elements including a plurality ofelectrode pads are formed; grinding a back side of the wafer to removean unnecessary part thereof; forming a via hole penetrating from theback side of the wafer to underneath of the plurality of electrode padsof the front side of the wafer; forming a passivation layer on wholesurfaces of the via hole and the back side of the wafer; removing thepassivation layer formed on the electrode pad; forming a via contact onthe via hole by filling the via hole with metal; forming a solder bumpon the via contact of the back side of the wafer; and dicing the waferand the transparent substrate.

In accordance with another aspect of the present invention, there isprovided a wafer level package of a CMOS image sensor, comprising: awafer where image sensor elements including a plurality of electrodepads are formed; a transparent substrate attached to a front side of thewafer; a via hole formed from a back side of the wafer to underneath ofa plurality of electrode pads of the front side of the wafer; apassivation layer formed on a remaining portion except the lower part ofthe electrode pads in the via hole and whole back side of the wafer; avia contact formed in the via hole; and a solder bump formed on the viacontact of the back side of the wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a camera module using a complementary metaloxide semiconductor (CMOS) image sensor (CIS) chip according to a priorart;

FIGS. 2 to 6 are cross-sectional views showing the process of Shellcasefor manufacturing the CIS package; and

FIGS. 7 to 16 are cross-sectional views showing a method of wafer levelpackaging of a CMOS image sensor using silicon via contacts inaccordance with the preferred embodiment of the present invention.

MODE FOR THE INVENTION

These and other features, aspects, and advantages of preferredembodiments of the present invention will be more fully described in thefollowing detailed description, taken accompanying drawings.

FIGS. 7 to 16 are cross-sectional views showing a method of wafer levelpackaging of a complementary metal oxide semiconductor (CMOS) imagesensor using silicon via contacts in accordance with the preferredembodiment of the present invention.

Referring to FIG. 7, through a predetermined manufacturing process, aplurality of electrode pads 301 for an electric connection to anexternal circuit and a sensing unit 302 for image sensing are formed ona wafer 300. The wafer 300 includes a plurality of chips and a dicingprocess for dividing chips from one another for packaging is performedafter completing the process for manufacturing chips. The chips aredivided from one another along the cutting lane.

Next, referring to FIG. 8, a transparent substrate 304 is attached onthe wafer 300. Desirably, the transparent substrate 304 is a glasssubstrate having a thickness ranging from 300 μm to 500 μm. Forattaching the transparent substrate 304, an epoxy layer 305 is formed toextend over the electrode pads 301 on the both sides of the cutting lane303. Further, a spacer 306 for securing space between the transparentsubstrate 304 and the wafer 300 is formed on the epoxy layer 305.Thereafter, the wafer 300 and the transparent substrate 304 are attachedto each other. Therefore, during the following manufacturing processes,the sensing unit 302 and the electrode pads 310 formed on the wafer 300are completely protected from any external foreign materials, resultingin a remarkably reduced defects.

Next, referring to FIG. 9, a back side of the wafere 300 is ground. Thegrinding process is performed in order to easily form a via hole in thewafer 300 in the subsequent process. Through the grinding process, thewafer 300 is ground, leaving a depth required for durability of thewafer 300. After the grinding process, a thickness of the wafer 300 isdesirably 50 μm to 100 μm.

And then, referring to FIG. 10, via holes 307 are formed penetratingfrom aback side of the wafer 300 to lower parts of the electrode pads301. The via hole 307 can be directly formed by means of dry etchingusing reactive ion etch (RIE). Otherwise, the via hole 307 can be madeby forming a partially non-penetrated hole and then removing theremaining part of the wafer 300 using a dry etching or a wet etching.Herein, a diameter of the via hole 307 may range from several tens of μmto thousands of μm, and preferably within 200 μm. Although a shape ofthe via hole 307 is basically circle, the via hole 307 can also havevarious shapes such as a triangle, a quadrangle or a polygon. Further, asize of the penetrating hole formed at the back side of the wafer 300can be larger, smaller or equal to that of underneath of the electrode301.

Thereafter, referring to FIG. 11, a passivation layer 308 for insulatingbetween electrodes is formed to cover etched surfaces of the via hole307 and the back side of the wafer 300. The passivation layer 308 isdesirably an oxide layer or a nitride layer. The passivation layer 308is desirably oxidized by nitric acid solution deposited usinglow-temperature plasma enhanced chemical vapor deposition (PECVD).

Next, referring to FIG. 12, the passivation layer 308 deposited on thebottom part of the via hole 307, i.e., the underneath of the electrodepad, is removed so that the electrode pads 301 are exposed.

Sequentially, referring to FIGS. 13 and 14, after a seed layer 309 isformed inside the via hole 307 using a sputtering process, a via contact310 is formed using a plating process or a printing process with solderpaste. Herein, any conductive materials including conductive metals suchas Au, Ag, Cu, Al, Ni, Cr and W or alloys thereof can be used.

Thereafter, referring to FIG. 15, a solder bump 311 is formed on theregion where the via contact 310 is formed on the back side of the wafer300. Although any conductive material can be used as the solder bump311, the solder bump 311 is desirably Cu, Au, an alloy of Ni/Au or analloy of Sn/Au.

Finally, referring to FIG. 16, chips are separated from one another bydicing the completed wafer 300 and the transparent substrate 304 alongthe cutting lane 303.

Through the above-mentioned processes in accordance with the preferredembodiment of the present invention, an image sensor chip is completed.Thereafter, the separated image sensor chip is connected to an externalcircuit by being attached to an FPC or a printed circuit board through asolder bump formed on a back side of a wafer. Thereafter, an imagedevice such as a camera is completed by assembling a lens and a lenshousing.

While the present invention has been described with respect to certainpreferred embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the scope of the invention as defined in the following claims.

INDUSTRIAL APPLICABILITY

By using silicon via contacts, the wafer level package of a CMOS imagesensor in accordance with the present invention has advantages asfollows: at first, a via contact connected from a back side of a waferto an electrode pad can be easily formed on a front side of the waferwhere image sensing elements including a sensing unit and the electrodepads are formed; secondly, a decrease in production yield due to theforeign materials coming into a sensing unit can be prevented bycovering with a transparent substrate, and forming a solder bump on avia contact exposed on a back side of the wafer and then connecting itto an external circuit through the back side, which has no image sensingelement; thirdly, a thickness of a completed image sensor module can bedecreased by removing unnecessary part of the wafer; and fourthly, achip scale package (CSP) of a semiconductor device including an imagesensor, which has a tendency to be smaller, can be effectively embodiedand, further, it can be applied to a multi chip module (MCM).

1. A method of wafer level packaging of a complementary metal-oxidesemi-conductor (CMOS) image sensor, the method comprising the steps of:attaching a transparent substrate to a front side of a wafer where imagesensor elements including a plurality of electrode pads are formed;grinding a back side of the wafer; forming a via hole penetrating fromthe back side of the wafer to underneath of the plurality of electrodepads of the front side of the wafer; forming a passivation layer onwhole surfaces of the via hole and the back side of the wafer; removingthe passivation layer formed on the electrode pad; forming a via contacton the via hole; forming a solder bump on the via contact of the backside of the wafer; and dicing the wafer and the transparent substrate.2. The method as recited in claim 1, before the step of attaching thetransparent substrate, further comprising the steps of: forming an epoxylayer to extend over the electrode pads in the both sides of a cuttinglane; and forming a spacer on an upper part of the epoxy layer.
 3. Themethod as recited in claim 1, wherein the via contact forming stepfurther includes the steps of: forming a seed layer in the via hole bysputtering; and filling the via hole with metal by printing of solderpaste or plating the metal on a metal layer in the via hole.
 4. Themethod as recited in claim 1, wherein a thickness of the transparentsubstrate is ranging from 300 μm to 500 μm.
 5. The method as recited inclaim 1, wherein a thickness of the wafer is ranging from 50 μm to 100μm after the grinding step.
 6. The method as recited in claim 1, whereinthe via hole is directly formed by dry etching using a reactive ion etch(RIE) or, after a partially non-penetrated hole is formed, the via holeis formed by removing the remaining part of the wafer which is notpenetrated using a dry etching or a wet etching.
 7. The method asrecited in claim 1, wherein the passivation layer is an oxide layer or anitride layer formed using oxidation in a nitric acid solution orlow-temperature plasma enhanced chemical vapor deposition (PECVD). 8.The method as recited in claim 1, wherein the via contact is made of oneconductive metal selected from a group consisting of Au, Ag, Cu, Al, Ni,Cr, W and the like or alloys thereof.
 9. The method as recited in claim1, wherein the solder bump is one of Cu, Au, an alloy of Ni/Au or analloy of Sn/Au.
 10. A wafer level package of a CMOS image sensor,comprising: a wafer where image sensor elements including a plurality ofelectrode pads are formed; a transparent substrate attached to a frontside of the wafer; a via hole formed from a back side of the wafer tounderneath of a plurality electrode pads of the front side of the wafer;a passivation layer formed on a remaining portion except the lower partof the electrode pads in the via hole and whole of the back side of thewafer; a via contact formed in the via hole; and a solder bump formed onthe via contact of the back side of the wafer.
 11. The wafer levelpackage of a CMOS image sensor as recited in claim 10, furthercomprising an epoxy layer and a spacer between the front side of thewafer and the transparent substrate.
 12. The wafer level package of aCMOS image sensor as recited in claim 10, wherein a thickness of thetransparent substrate ranges from 300 μm to 500 μm.
 13. The wafer levelpackage of a CMOS image sensor as recited in claim 10, wherein athickness of the wafer ranges from 50 μm to 100 μm.
 14. The wafer levelpackage of a CMOS image sensor as recited in claim 10, wherein thepassivation layer is made of an oxide layer or a nitride layer.
 15. Thewafer level package of a CMOS image sensor as recited in claim 10,wherein the via contact is made of one conductive metal selected from agroup consisting of Au, Ag, Cu, Al, Ni, Cr, W or alloys thereof.
 16. Thewafer level package of a CMOS image sensor as recited in claim 10,wherein the solder bump is one of an alloy of Cu, Au, Ni/Au or an alloyof Sn/Au.